In the previous literature, the introduction of the virtual space vector concept for the three-level three-leg neutral-point-clamped converter has led to the definition of pulsewidth modulation (PWM) strategies guaranteeing the dc-link capacitor voltage balance under any type of load, with the only requirement being that the addition of the three phase currents equals zero. This paper presents the definition of the virtual space vectors for the general case of an n-level converter, suggests guidelines for designing virtual-space-vector PWM strategies, and provides the expressions of the phase duty-ratio waveforms corresponding to this family of PWMs. Modulations defined upon these vectors enable the use of diode-clamped topologies with passive front-ends. The performance of these converters operated with the proposed PWMs is compared to the performance of alternative designs through analysis, simulation and experiments.